`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// átalakítja a mem_countert digitté
//
//////////////////////////////////////////////////////////////////////////////////
module digit(
		input clk, rst,
		input [2:0] folyamat,
		input [7:0] w_address,	
		input [7:0] r_address,

		output [3:0] digit1,
		output [3:0] digit2,
		output [3:0] digit3,
		output [3:0] digit4

    );
reg [3:0] digit1_w = 4'd0;
reg [3:0] digit2_w = 4'd0;
reg [3:0] digit3_w = 4'd2;
reg [3:0] digit4_w = 4'd0;

reg mehet = 0;
reg [7:0] tmp;

	always @(posedge clk)
	begin
		if(folyamat == 3'd5)
		begin
			tmp <= 8'd0;
			mehet <= 0;
		end
		else if(w_address != tmp)
		begin
			tmp <= w_address;
			mehet <= 1;
		end
		
		else
			mehet <= 0;
	end	


wire digit2_en_w;
wire digit3_en_w;
wire digit4_en_w;
   
assign digit2_en_w = (digit1_w == 4'd0);
assign digit3_en_w = ((digit2_w == 4'd0) & digit2_en_w);
assign digit4_en_w = ((digit3_w == 4'd0) & digit3_en_w);
   
   always @(posedge clk)
   begin
      if (/*rst ||*/ (folyamat == 3'd5))
         digit1_w <= 4'd0;
      else
         if (mehet && (folyamat!=3'd5))
         begin
            if (digit2_en_w)
               digit1_w <= 4'd9;
            else
               digit1_w <= digit1_w - 1;
         end
   end
   
   always @(posedge clk)
   begin
      if (/*rst ||*/ (folyamat == 3'd5))
         digit2_w <= 4'd0;
      else
         if ((mehet) && (digit2_en_w) && (folyamat!=3'd5))
         begin
            if (digit3_en_w)
               digit2_w <= 4'd9;
            else
               digit2_w <= digit2_w - 1;
         end
   end
   
   always @(posedge clk)
   begin
      if (/*rst ||*/ (folyamat == 3'd5))
         digit3_w <= 4'd2;
      else
         if ((mehet) && (digit3_en_w) && (folyamat!=3'd5))
         begin
            if (digit4_en_w)
               digit3_w <= 4'd9;
            else
               digit3_w <= digit3_w - 1;
         end
   end
   
   always @(posedge clk)
   begin
      if (/*rst || */(folyamat == 3'd5) )
         digit4_w <= 4'd0;
      else
         if ((mehet) && (digit4_en_w) && (folyamat!=3'd5))
         begin
            if (digit4_w == 4'd0)
               digit4_w <= 4'd0;
            else
               digit4_w <= digit4_w - 1;
         end
   end
	

reg mehet2 = 0;
reg [7:0] tmp2;

	always @(posedge clk)
	begin
		if(folyamat == 3'd5)
		begin
			tmp2 <= 8'd0;
			mehet2 <= 0;
		end
		else if(r_address != tmp2)
		begin
			tmp2 <= r_address;
			mehet2 <= 1;
		end
		
		else
			mehet2 <= 0;
	end	
	
// 0 0 0 0 -ról felfele 200-ig	
reg [3:0] digit1_r = 4'd0;
reg [3:0] digit2_r = 4'd0;
reg [3:0] digit3_r = 4'd0;
reg [3:0] digit4_r = 4'd0;
	
assign digit2_en_r = (digit1_r == 4'd9);
assign digit3_en_r = ((digit2_r == 4'd9) & digit2_en_r);
assign digit4_en_r = ((digit3_r == 4'd9) & digit3_en_r);
   
   always @(posedge clk)
   begin
      if (rst || (folyamat == 3'd5) || (folyamat == 3'd1))
         digit1_r <= 4'd0;
      else
         if (mehet2 && (folyamat!=3'd5))
         begin
            if (digit2_en_r)
               digit1_r <= 4'd0;
            else
               digit1_r <= digit1_r + 1;
         end
   end
   
   always @(posedge clk)
   begin
      if (rst || (folyamat == 3'd5) || (folyamat == 3'd1))
         digit2_r <= 4'd0;
      else
         if ((mehet2) && (digit2_en_r) && (folyamat!=3'd5))
         begin
            if (digit3_en_r)
               digit2_r <= 4'd0;
            else
               digit2_r <= digit2_r + 1;
         end
   end
   
   always @(posedge clk)
   begin
      if (rst || (folyamat == 3'd5) || (folyamat == 3'd1))
         digit3_r <= 4'd0;
      else
         if ((mehet2) && (digit3_en_r) && (folyamat!=3'd5))
         begin
            if (digit4_en_r)
               digit3_r <= 4'd0;
            else
               digit3_r <= digit3_r + 1;
         end
   end
   
   always @(posedge clk)
   begin
      if (rst || (folyamat == 3'd5) || (folyamat == 3'd1))
         digit4_r <= 4'd0;
      else
         if ((mehet2) && (digit4_en_r) && (folyamat!=3'd5))
         begin
            if (digit4_r == 4'd5)
               digit4_r <= 4'd0;
            else
               digit4_r <= digit4_r + 1;
         end
   end

assign digit1 = (folyamat == 3'd3) ? digit1_w : ( (folyamat == 3'd4) ? digit1_r : 4'd0);
assign digit2 = (folyamat == 3'd3) ? digit2_w : ( (folyamat == 3'd4) ? digit2_r : 4'd0);
assign digit3 = (folyamat == 3'd3) ? digit3_w : ( (folyamat == 3'd4) ? digit3_r : 4'd0);
assign digit4 = (folyamat == 3'd3) ? digit4_w : ( (folyamat == 3'd4) ? digit4_r : 4'd0);

endmodule

