robotkar6 Project Status
Project File:	robotkar6.ise	Implementation State:	Programming File Generated
Module Name:	r_top	Errors:	No Errors
Target Device:	xc3s250e-4tq144	Warnings:	28 Warnings
Product Version:	ISE 11.1	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Setup: 0, Hold: 0) (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	640	4,896	13%
Number of 4 input LUTs	1,704	4,896	34%
Number of occupied Slices	1,072	2,448	43%
Number of Slices containing only related logic	1,072	1,072	100%
Number of Slices containing unrelated logic	0	1,072	0%
Total Number of 4 input LUTs	1,919	4,896	39%
Number used as logic	1,704
Number used as a route-thru	215
Number of bonded IOBs	63	108	58%
IOB Flip Flops	4
Number of BUFGMUXs	1	24	4%
Average Fanout of Non-Clock Nets	3.95

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	V ápr. 18 11:40:09 2010	0	28 Warnings	19 Infos
Translation Report	Current	V ápr. 18 11:40:15 2010	0	0	0
Map Report	Current	V ápr. 18 11:40:22 2010	0	0	2 Infos
Place and Route Report	Current	V ápr. 18 11:40:48 2010	0	0	3 Infos
Power Report
Post-PAR Static Timing Report	Current	V ápr. 18 11:40:53 2010	0	0	3 Infos
Bitgen Report	Current	V ápr. 18 11:41:02 2010	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 04/20/2010 - 17:45:35