Simulation and Formal Verification for Improving Safety of PLC Programs

A tétel rövid nézete
dc.creatorGalvão, Joel
dc.creatorMachado, José
dc.date2016-09-14
dc.date.accessioned2020-09-11T08:33:49Z
dc.date.available2020-09-11T08:33:49Z
dc.descriptionThe use of analysis techniques for improving quality of software for industrial controllers is widely used. Mainly Simulation and Formal Verification can be used as complementary techniques improving dependability of mechatronic systems behavior. In this paper there are used Simulation and Formal Verification for guaranteeing safe software for Programmable Logic Controllers, mainly related with using Function blocks of IEC 61131-3 standard. For studying, simulating and verifying behavior of those blocks are used timed automata, as modeling formalism, and UPPAAL, as tool for simulation and Formal Verification purposes.
dc.formatapplication/pdf
dc.identifierhttps://ojs.lib.unideb.hu/rIim/article/view/3848
dc.identifier10.17667/riim.2016.1-2/9.
dc.identifier.urihttp://hdl.handle.net/2437/295755
dc.languageeng
dc.publisherDebreceni Egyetem
dc.relationhttps://ojs.lib.unideb.hu/rIim/article/view/3848/3728
dc.sourceRecent Innovations in Mechatronics; Vol. 3 No. 1-2. (2016); 1-6.
dc.sourceRecent Innovations in Mechatronics; Évf. 3 szám 1-2. (2016); 1-6.
dc.source2064-9622
dc.subjectIEC 61131-3
dc.subjectSimulation
dc.subjectFormal Verification
dc.subjectDependable Mechatronic Systems
dc.titleSimulation and Formal Verification for Improving Safety of PLC Programs
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/publishedVersion
dc.typePeer-reviewed Article
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Recent Innovations in Mechatronics (OJS)