Simulation and Formal Verification for Improving Safety of PLC Programs

A tétel rövid nézete
dc.contributor.authorGalvão, Joel
dc.contributor.authorMachado, José
dc.date.accessioned2020-09-11T08:33:49Z
dc.date.available2020-09-11T08:33:49Z
dc.date.issued2016-09-14
dc.description.abstractThe use of analysis techniques for improving quality of software for industrial controllers is widely used. Mainly Simulation and Formal Verification can be used as complementary techniques improving dependability of mechatronic systems behavior. In this paper there are used Simulation and Formal Verification for guaranteeing safe software for Programmable Logic Controllers, mainly related with using Function blocks of IEC 61131-3 standard. For studying, simulating and verifying behavior of those blocks are used timed automata, as modeling formalism, and UPPAAL, as tool for simulation and Formal Verification purposes.en
dc.formatapplication/pdf
dc.identifier.citationRecent Innovations in Mechatronics, Vol. 3 No. 1-2. (2016) , 1-6.
dc.identifier.doihttps://doi.org/10.17667/riim.2016.1-2/9.
dc.identifier.eissn2064-9622
dc.identifier.issue1-2.
dc.identifier.jtitleRecent Innovations in Mechatronics
dc.identifier.urihttps://hdl.handle.net/2437/295755en
dc.identifier.volume3
dc.languageen
dc.relationhttps://ojs.lib.unideb.hu/rIim/article/view/3848
dc.rights.accessOpen Access
dc.rights.ownerby the authors
dc.subjectIEC 61131-3en
dc.subjectSimulationen
dc.subjectFormal Verificationen
dc.subjectDependable Mechatronic Systemsen
dc.titleSimulation and Formal Verification for Improving Safety of PLC Programsen
dc.typefolyóiratcikkhu
dc.typearticleen
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