Simulation and Formal Verification for Improving Safety of PLC Programs

A tétel rövid nézete
dc.contributor.authorJoel, Galvão
dc.contributor.authorJosé, Machado
dc.date.accessioned2016-09-14T09:50:56Z
dc.date.available2016-09-14T09:50:56Z
dc.date.issued2016-09-14
dc.description.abstractThe use of analysis techniques for improving quality of software for industrial controllers is widely used. Mainly Simulation and Formal Verification can be used as complementary techniques improving dependability of mechatronic systems behavior. In this paper there are used Simulation and Formal Verification for guaranteeing safe software for Programmable Logic Controllers, mainly related with using Function blocks of IEC 61131-3 standard. For studying, simulating and verifying behavior of those blocks are used timed automata, as modeling formalism, and UPPAAL, as tool for simulation and Formal Verification purposes.hu_HU
dc.identifier.doi10.17667/riim.2016.1-2/9.hu_HU
dc.identifier.issn2064-9622hu_HU
dc.identifier.issue1-2hu_HU
dc.identifier.urihttp://hdl.handle.net/2437/230431
dc.identifier.volume3hu_HU
dc.language.isoenhu_HU
dc.publisherDUPresshu_HU
dc.publisher.placeDebrecenhu_HU
dc.rightsNevezd meg! - Ne add el! - Ne változtasd! 2.5 Magyarország*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/2.5/hu/*
dc.subjectIEC 61131-3hu_HU
dc.subjectSimulationhu_HU
dc.subjectFormal Verificationhu_HU
dc.subjectDependable Mechatronic Systemshu_HU
dc.titleSimulation and Formal Verification for Improving Safety of PLC Programshu_HU
dc.typeArticlehu_HU
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Recent Innovations in Mechatronics