Modeling and simulation of FPGA-based redundant digital systems

dc.contributor.authorSzász, Csaba
dc.contributor.statusnemhu_HU
dc.date.accessioned2021-04-07T07:03:15Z
dc.date.available2021-04-07T07:03:15Z
dc.date.issued2020-04-01
dc.description.abstractReliability is one of the most important criteria that characterize last generation digital systems. In a wide range of applications the required reliability level is achieved by using hardware redundant configurations. Perhaps their most common form is the triple modular redundancy (TMR) based on a majority voting structure. Researchers that use this strategy make a major assumption: in fault-free operation mode the outputs of these digital systems match in all. This paper proves that synchronization and matching in all the outputs of such systems is not such a trivial problem. In this endeavor FPGA-based (Field Programmable Gate Arrays) redundant topologies are considered for study and experiments. Upon these structures specially conceived redundant models have been developed and simulated. The results outline that synchronization of complex digital systems is a difficult engineering undertaking and any initial assumption should be managed with the adequate circumspection.hu_HU
dc.identifier.doi10.1556/1848.2020.00011hu_HU
dc.identifier.issn2062-0810
dc.identifier.issue1hu_HU
dc.identifier.jtitleInternational Review of Applied Sciences and Engineering
dc.identifier.urihttp://hdl.handle.net/2437/305289
dc.identifier.urlhttps://akjournals.com/view/journals/1848/11/1/article-p73.xmlhu_HU
dc.identifier.volume11hu_HU
dc.language.isoenhu_HU
dc.publisherAkadémiai Kiadóhu_HU
dc.subjectredundant systemhu_HU
dc.subjectreliabilityhu_HU
dc.subjectdigital voterhu_HU
dc.subjectFPGA processorhu_HU
dc.subjectoutputs matchinghu_HU
dc.titleModeling and simulation of FPGA-based redundant digital systemshu_HU
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