Discovering technical properties and software-economy readiness of RISC-V architecture

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dc.contributor.advisorAdamkó, Attila Tamás
dc.contributor.advisorPap, Zsigmond
dc.contributor.authorDidberidze, Giorgi
dc.contributor.departmentDE--Informatikai Karhu_HU
dc.date.accessioned2022-05-04T13:49:09Z
dc.date.available2022-05-04T13:49:09Z
dc.date.created2022-05-04
dc.description.abstractIn this research, I would like to present RISC-V, which is extensible, royalty free and open Reduced Instruction Set Computer (RISC) ISA. It means that any chip manufacturer can create CPUs that use this instruction set using preferred optional extensions without having to pay royalties. With its open license business model, anyone can leverage the IP (Intellectual Property) contributed and produced by RISC-V International. It is an emerging ISA that is driven through open collaboration, bringing together different companies, industries, and geographies. RISC-V is suitable for a wide range of applications, from simple microcontrollers to high-performance CPUs. Full Instruction Set Manual can be accessed at the official website of RISC-V International. Therefore, in this research, I will outline the fundamental properties of the RISC-V ISA in order to better comprehend and analyze its applications on a wide scale.hu_HU
dc.description.courseComputer Sciencehu_HU
dc.description.degreeBSc/BAhu_HU
dc.format.extent39hu_HU
dc.identifier.urihttp://hdl.handle.net/2437/332277
dc.language.isoenhu_HU
dc.subjectRISC-Vhu_HU
dc.subjectarchitecturehu_HU
dc.subject.dspaceDEENK Témalista::Informatikahu_HU
dc.titleDiscovering technical properties and software-economy readiness of RISC-V architecturehu_HU
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