Reliability is one of the most important criteria that characterize last generation digital systems. In a wide range of applications the required reliability level is achieved by using hardware redundant configurations. Perhaps their most common form is the triple modular redundancy (TMR) based on a majority voting structure. Researchers that use this strategy make a major assumption: in fault-free operation mode the outputs of these digital systems match in all. This paper proves that synchronization and matching in all the outputs of such systems is not such a trivial problem. In this endeavor FPGA-based (Field Programmable Gate Arrays) redundant topologies are considered for study and experiments. Upon these structures specially conceived redundant models have been developed and simulated. The results outline that synchronization of complex digital systems is a difficult engineering undertaking and any initial assumption should be managed with the adequate circumspection.